Pxaregs

To see NSSP registers with pxaregs add the following to in gumstix-buildroot/build_arm_nofpu/pxaregs-1.14/pxaregs.c { "SSCR0",             0x41400000, 0, 0xffffffff, 'x', "SSP Control Register 0" }, { "DSS",               0x41400000, 0, 0x0000000f, 'x', " data size select" }, { "FRF",               0x41400000, 4, 0x00000003, 'x', " frame format" }, { "SSE",               0x41400000, 7, 0x00000001, 'x', " port enable" }, { "SCR",               0x41400000, 8, 0x00000fff, 'x', " serial clock rate" }, { "EDDD",              0x41400000,20, 0x00000001, 'x', " extended data size select" },

{ "SSCR1",             0x41400004, 0, 0xffffffff, 'x', "SSP Control Register 1" }, { "RIE",               0x41400004, 0, 0x00000001, 'x', " receive FIFO interrupt enable" }, { "TIE",               0x41400004, 1, 0x00000001, 'x', " transmit FIFO interrupt enable" }, { "LBM",               0x41400004, 2, 0x00000001, 'x', " loopback mode (test-mode bit only)" }, { "SPO",               0x41400004, 3, 0x00000001, 'x', " Motorola SPI SSPSCLKx polarity" }, { "SPH",               0x41400004, 4, 0x00000001, 'x', " Motorola SPI SSPSCLKx phase" }, { "MWDS",              0x41400004, 5, 0x00000001, 'x', " Microwire transmit data size" }, { "TFT",               0x41400004, 6, 0x0000000f, 'x', " transmit FIFO threshold" }, { "RFT",               0x41400004,10, 0x0000000f, 'x', " receive FIFO threshold" }, { "EFWR",              0x41400004,14, 0x00000001, 'x', " enable FIFO write/read (test mode bit)" }, { "STRF",              0x41400004,15, 0x00000001, 'x', " select FIFO for EFWR (test mode bit only)" }, //{ "reserved",        0x41400004,16, 0x00000007, 'x', "" }, { "TINTE",             0x41400004,19, 0x00000001, 'x', " receiver timeout interrupt enable" }, { "RSRE",              0x41400004,20, 0x00000001, 'x', " receive service request enable" }, { "TSRE",              0x41400004,21, 0x00000001, 'x', " transmit service request enable" },

//{ "reserved",        0x41400004,22, 0x00000001, 'x', "" }, { "RWOT",              0x41400004,23, 0x00000001, 'x', " receive without transmit" }, { "SFRMDIR",           0x41400004,24, 0x00000001, 'x', " frame direction" }, { "SCLKDIR",           0x41400004,25, 0x00000001, 'x', " serial bit rate clock direction" }, //{ "reserved",        0x41400004,26, 0x00000003, 'x', "" }, { "SCFR",              0x41400004,28, 0x00000001, 'x', " slave clock free running" }, { "EBCEI",             0x41400004,29, 0x00000001, 'x', " bit count error interrupt mask" }, { "TTE",               0x41400004,30, 0x00000001, 'x', " transmit high-Z enable" }, { "TTELP",             0x41400004,31, 0x00000001, 'x', " transmit high-Z later phase" },

{ "SSPSP",             0x4140002c, 0, 0xffffffff, 'x', "SSP Programmable Serial Protocol Register" }, { "SCMODE",            0x4140002c, 0, 0x00000003, 'x', " serial bit-rate clock mode" }, { "SFRMP",             0x4140002c, 2, 0x00000001, 'x', " serial frame polarity" }, { "ETDS",              0x4140002c, 3, 0x00000001, 'x', " end of transfer data state" }, { "STRTDLY",           0x4140002c, 4, 0x00000007, 'x', " three-bit start delay field" }, { "DMYSTRT",           0x4140002c, 7, 0x00000003, 'x', " dummy start" }, { "SFRMDLY",           0x4140002c, 9, 0x0000003f, 'x', " serial frame delay" }, { "SFRMWDTH",          0x4140002c,16, 0x0000003f, 'x', " serial frame width" }, { "DMYSTOP",           0x4140002c,23, 0x00000003, 'x', " dummy stop" }, //{ "reserved",        0x4140002c,25, 0x0000003f, 'x', "" },

{ "SSTO",              0x41400028, 0, 0xffffffff, 'x', "SSP Time Out Register" }, { "TIMEOUT",           0x41400028, 0, 0x00ffffff, 'x', " timeout" },

{ "SSITR",             0x4140000c, 0, 0xffffffff, 'x', "SSP Interrupt Test Register" }, //{ "reserved",        0x4140000c, 0, 0x0000001f, 'x', "" }, { "TTFS",              0x4140000c, 5, 0x00000001, 'x', " test transmit fifo service request" }, { "TRFS",              0x4140000c, 6, 0x00000001, 'x', " test receive fifo service request" }, { "TROR",              0x4140000c, 7, 0x00000001, 'x', " test receive fifo overrun" }, //{ "reserved",        0x4140000c, 8, 0x00ffffff, 'x', " reserved" },

{ "SSSR",              0x41400008, 0, 0xffffffff, 'x', "SSP Status Register" }, //{ "reserved",        0x41400008, 0, 0x00000003, 'x', "" }, { "TNF",               0x41400008, 2, 0x00000001, 'x', " transmit fifo not full" }, { "RNE",               0x41400008, 3, 0x00000001, 'x', " receive fifo not empty" }, { "BSY",               0x41400008, 4, 0x00000001, 'x', " ssp busy" }, { "TFS",               0x41400008, 5, 0x00000001, 'x', " transmit fifo service request" }, { "RFS",               0x41400008, 6, 0x00000001, 'x', " receive fifo service request" }, { "ROR",               0x41400008, 7, 0x00000001, 'x', " receive fifo overrun" }, { "TFL",               0x41400008, 8, 0x0000000f, 'x', " transmit fifo level" }, { "RFL",               0x41400008,12, 0x0000000f, 'x', " receive fifo level" }, //{ "reserved",        0x41400008,16, 0x00000007, 'x', "" }, { "TINT",              0x41400008,19, 0x00000001, 'x', " receiver timeout interrupt" }, //{ "reserved",        0x41400008,20, 0x00000001, 'x', "" }, { "TUR",               0x41400008,21, 0x00000001, 'x', " transmit fifo underrun" }, { "CSS",               0x41400008,22, 0x00000001, 'x', " clock synchronization status" }, { "BCE",               0x41400008,23, 0x00000001, 'x', " bit count error" }, //{ "reserved",        0x41400008,24, 0x000001ff, 'x', "" },

{ "SSDR",              0x41400010, 0, 0xffffffff, 'x', "SSP Data Register" },