Template:FAQ/Questions/verdex pinout changes

What pinouts changes were made on the verdex 60-pin connector as compared the 60-pin connector of the basix and connex motherboards ?
• JTAG will not be on the verdex 60 pin connector but will be on test pads on the 24-120 side of the verdex motherboard.

• DREQ0 is replaced with GPIO101 SDATA_IN1 is replaced with CLK_32

• There are only 3 UARTs on the PXA270, but there were 4 UARTS on the 60-pin Hirose.

• Reconciliation: we consider the BT and HW UARTs as redundant. Gumstix decided to put the BT-UART pins where the HW-UART pins were and to drop the BT pins (which are in the place of the old JTAG pins).

• Added pins:

- LDD_16, LDD_17 for increased LCD resolution

- GPIO_41 for OTG_ID

- SYS_EN for daughtercard power management (will enable powering down daughtercads in sleep mode)